1. Field of the Invention
The present invention relates in general to a semiconductor device and method for fabricating the same. More particularly, it relates to a vertical split gate flash memory cell that increases integration with ICs.
2. Description of the Related Art
Non-volatile memory, such as flash memory, stores data regardless of electrical power supplied, and reads and writes data by controlling a threshold voltage of a control gate. Conventionally, flash memory includes a floating gate and a control gate. The floating gate stores charge and the control gate reads and writes data. In addition, the floating gate is located under the control gate and is not connected to external circuit, and the control gate connects to the word line. One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, memory erasure is fast, and normally takes just 1 to 2 seconds for the complete removal of a whole block of memory. Therefore, in recent years, it has been widely applied to consumer electronics devices, such as digital cameras, mobile phones, personal stereos, and laptops.
There is much interest in reducing the size of individual semiconductor devices to increase their density on an integrated circuit (IC) chip. This reduces size and power consumption of the chip, and allows faster operation. In order to achieve a memory cell with a minimum size, the gate length (line width) in a conventional transistor must be reduced to decrease the lateral dimension of the memory cell. However, the conventional process for fabricating flash memory usually uses photomasks to define the devices. Since the precision of the photomasks is limited, misalignment usually occurs for devices with a smaller line width. This causes open circuits or short circuits, and the electrical properties of the flash memory fail. Therefore, the device size of the conventional flash memory is limited by the design rule, so it is difficult to shrink the device size. In addition, short channel effect and hot carrier effect occurs when the line width is shrink, thereby reducing the reliability of devices.
Accordingly, an object of the invention is to provide a novel vertical split gate flash memory cell to increase the integration of ICs by decreasing the lateral dimension of the memory cell.
Another object of the invention is to provide a novel method for fabricating a vertical split gate flash memory cell to prevent short channel effect, thereby increasing the reliability of devices.
According to one aspect, the invention provides a split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation between the floating gate and the control gate. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the floating gate to serve as source and drain regions with the first doping region. The memory cell further includes an insulating layer, a conductive stud, and a gate structure. The insulating layer is disposed over the first doping region. The conductive stud is disposed on the control gate and insulated from the first doping region by an insulating spacer. The gate structure is disposed on the conductive stud to serve as a word line.
According to another aspect, the invention provides a method for fabricating a vertical split gate flash memory cell. First, a substrate having a first trench and a second trench is provided. Next, a conformable floating gate oxide layer is formed over the sidewall and the bottom of each lower portion of the trench. Next, a floating gate is fanned over the floating gate oxide layer in each of the lower portion of the trenches. Next, a tunnel oxide layer is formed on the floating gate. Next, a conformable control gate oxide layer is formed over the sidewall of each upper portion of the trench. Next, a control gate is formed on the inter-gate dielectric layer. Next, ion implantation is performed in the substrate adjacent to the floating gate to form a second doping region. Finally, ion implantation is performed in the substrate adjacent to the control gate to form a first doping region. Moreover, after the control gate is formed, a conductive stud and an insulating spacer are formed on the control gate, wherein the conductive stud is insulated from the first doping region by the insulating spacer. Next, an insulating layer is formed over the first doping region. Next, parts of the conductive stud, the insulating spacer, the control gate, the control gate oxide layer, the tunnel oxide layer, the floating gate, and the floating gate oxide layer in the fist trench are removed to form a third trench. Thereafter, an isolation structure is formed in the third trench. Next, a plurality of gate structures is formed over the insulating layer and the trenches.